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M5913
COMBINED SINGLE CHIP PCM CODEC AND FILTER
SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE -LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS LOW POWER DISSIPATION: 0.5mW POWER DOWN 70mW OPERATING EXCELLENT POWER SUPPLY REJECTION DESCRIPTION The M5913 is fully integrated PCM (pulse code modulation) codecs and transmit/receive filter using CMOS silicon gate technology. The primary applications for the M5913 are telephone systems : - Switching - M5913-Digital PBX's and Central BLOCK DIAGRAM
DIP 20 ORDERING NUMBER: M5913B1
Office Switching Systems - Concentration - M5913 Subscriber Carrier and Concentrators. The wide dynamic range (78dB) and the minimal conversion time make it ideal products for other applications such as: - Voice Store and Forward - Secure Communications Systems - Digital Echo Cancellers - Satellite Earth Stations.
December 1993
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M5913
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VBB GRDD, GRDA VI/O VO DIG Ptot Tstg Parameter With Respect GRDD, GRDA = 0V With Respect GRDD, GRDA = 0V In Such Case : 0 VCC + 7V, - 7V VBB 0V Analog Inputs, Analog Outputs and Digital Inputs Digital Outputs Total Power Dissipation Storage Temperature Range Value - 0.6 to 7 - 0.6 to - 7 0.3 VBB - 0.3 VIN/VOUT VCC + 0.3 GRDD - 0.3 VOUT VCC + 0.3 1 -65 to 150 Unit V V V V V W C
PIN CONNECTION (Top view)
PIN NAMES
Symbol VBB PWRO+, PWROGSR PDN CLKSEL LOOP SIG R DCLKR DR FSR GRDD VCC Power (-5V) Power Amplifier Outputs Gain Setting Input for receive Channel Power Pown Select Master Clock Select Analog Loop Back Signaling Bit Output Receive Data Rate Clock Receive Channel Input Receive Frame Synchronization Clock Digital Ground Power (+5V) Parameter Symbol GSX VFXI-, VFXI+ GRDA NC SIG X ASEL TSX DCLKX DX FSX CLKX CLKR Gain Control Analog Inputs Analog Ground No Connected Transmit Digital Signaling Input or A-law Select Digital Output - Timeslot Strobe Transmit Data Rate Clock Transmit (Digital) Output Transmit Frame Synchronization Clock Transmit Master Clock Receive Master Clock Parameter
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PIN DESCRIPTION
Symbol VBB PWRO+ PWRO GSR PDN CLKSEL Function Most Negative Supply. Input voltage is -5 volts 5%. Non-inverting Output of Power Amplifier. Can drive transformer hybrids or high impedance loads directly in either a differential or single ended configuration. Inverting Output of Power Amplifier. Functionally identical and complementary to PWRO+. Input to the gain Setting Network on the Output Power Amplifier, Transmission level can be adjusted over a 12dB range depending on the voltage at GSR. Power Down Select. When PDN is TTL high, the device is active.When low, the device is powered down. input which must be pinstrapped to reflect the master clock frequency at CLKX, CLKR. CLKSEL = VBB 2.048MHz CLKSEL = GRDD 1.544MHz CLKSEL = VCC 1.536MHz Analog Loopback. When this pin is TTL high, the receive output (PWRO+) is internally connected to VFXI+, GSR is internally connected to PWRO-, and VFXI- is internally connected to GSX. A 0dBm0 digital signal input at DR is returned as a +3dBm0 digital signal output at DX. Signalling Bit Output, Receive Channel. In fixed data rate mode. SIGR outputs the logical state of the eighth bit of the PCM word in the most recent signaling frame. Selects the fixed or variable data rate mode. When DCLKR is connected to VBB, the fixed data rate mode is selected. When DCLKR is not connected to VBB, the device operates in the variable data rate mode. In this mode DCLKR becomes the receive data clock wich operates at TTL levels from 64kB to 4.096MB data rates Receive PCM Input. PCM data is clocked in on this lead on eight consecutive negative transitions of the receive data clock: CLKR in the fixed data rate mode and DCLKR in variable data rate mode. 8kHz frame synchronization clock input/timeslot enable, receive channel. A multifunction input which in fixed data rate mode distinguishes between signaling and non-signaling frames by means of a double or single wide pulse respectively. In variable data rate mode this signal must remain high for the entire length of the timeslot. The receive channel enters the standby state whenever FSR is TTL low for 30 miliseconds Digital Ground for all Internal Logic Circuits. Not internally tied to GRDA. Receive master and data clock for the fixed data rate mode; receive master clock only in variable data rate mode. Transmit master and data clock for the fixed data rate mode; transmit master clock only in variable data rate mode. 8kHz frame synchronization clock input/timeslot enable, transmit channel. Operates independently but in an analogous manner to FSR. The transmit channel enters the standby state whenever FSX is TTL low for 30 milliseconds. Transmit PCM Output. PCM data is clocked out on this lead on eight consecutive positive transitions of the transmit data clock : CLK in fixed data rate mode and DCLKX in variable data rate mode. Transmit channel timeslot strobe (output) or data clock (input) for the transmit channel. In fixed data rate mode, this pin becomes the transmit data clock which operates at TTL levels from 64kB to 4.096MB data rates. A dual purpose selects -law and pin. When connected to VBB. A law operation is selected. When it is not connected to VBB pin is a TTL level input for signaling operation. This input is transmitted as the eighth bit of the PCM word during signaling frames on the DX lead. Not Connected. Analog ground return for all internal voice circuits. Not internally connected to GRDD. Non inverting analog input to uncommitted transmit operational amplifier. Inverting analog input to uncommitted transmit operational amplifier. Output terminal of on-chip uncommitted op amp. Internally, this is the voice signal input to the transmit filter. Most positive supply ; input voltage is + 5 volts 5%
LOOP
SIGR DCLKR
DR FSR
GRDD CLKR CLKX FSX
DX
TSX/DCLKX
SIG X/ASEL
NC GRDA VFXI+ VFXIGSX VCC
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M5913
FUNCTIONAL DESCRIPTION The M5913 provides the analog-to-digital and the digital-to-analog conversion and the transmit and receive filtering necessary to interface a full duplex (4 wires) voice telephone circuit with the PCM highway of a time division multiplexed (TDM) system. It is intended to be used at the analog termination of a PCM line. The following major functions are provided : Bandpass filtering of the analog signals prior to encoding and after decoding Encoding and decoding of voice and call progress information Encoding and decoding of the signaling and supervision information GENERAL OPERATION System Reliability Features The combo-chip can be powered up by pulsing FSX and/or FSR while a TTL high voltage is applied to PDN, provided that all clocks and supplies are connected. The M5913 has internal resets on power up (or when VBB or VCC are re-applied) in order to ensure validity of the digital outputs and thereby maintain integrity of the PCM highway. On the transmit channel, digital outputs DX and TS X are held in a high impedance state for approximately four frames (500s) after power up or application of VBB or VCC. After this delay, DX and TSX will be functional and will occur in the proper timeslot. The analog circuits on the transmit side require approximately 40 milliseconds to reach their equilibrium value due to the autozero circuit setting time. Thus, valid digital information, such as for on/off hook detection, is available almost immediately, while analog information is available after some delay. On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up or application of VBB or VCC, SIGR will remain low thereafter until it is updated by a signaling frame. To further enhance system reliability, TS X and DX will be placed in a high impedance state approximately 20s after an interruption of CLKX. SimiTable 1: Power Down Methods
Device Status Power Down Mode Stand-by Mode Power Down Methods PDN = TTL low FSX and FSR are TTL low Digital Outputs Status TSX and DX are placed in a high impedance state and SIG R is placed in a TTL low state within 10s. TSX and DX are placed in a high impedance state and SIG R is placed in a TTL low state 30ms after FSX and FSR are removed. TSX and DX are placed in a high impedance state within 30ms. SIG R is placed in a TTL low state within 30ms.
larly SIGR will be held low approximately 20s after an interruption of CLKR. These interruptions could possibly occur with some kind of fault condition. Power Down And Standby Modes To minimize power consumption, two power down modes are provided in which most M5913 functions are disabled. Only the power down, clock, and frame sync buffers, which are required to power up the device, are enabled in these modes. As shown in table 1, the digital outputs on the appropriate channels are placed in a high impedance state until the device returns to the active mode. The Power Down mode utilizes an external control signal to the PDN pin. In this mode, power consumption is reduced to an average of 0.5mW. The device is active when the signal is high and inactive when it is low. In the absence of any signal, the PDN pin floats to TTL high allowing the device to remain active continuously. The Standby mode leaves the user an option of powering either channel down separately or powering the entire down by selectively removing FSX and/or FSR. With both channels in the standby state, power consumption is reduced to an average of 1mW. If transmit only operation is desired, FSX should be applied to the device while FSR is held low. Similarly, if receive only operation is desired, FSR should be applied while FSX is held low. Fixed Data Rate Mode Fixed data rate timing, is selected by connecting DCLKR to VBB. It employs master clock CLKX, and CLKR, frame synchronization clocks FSX and FSR , and output TS X. CLKX, and CLKR, serve both as the master clock to operate the codec and filter sections and bit clocks to clock the data in and out from the PCM highway. FSX and FSR are 8kHz inputs which set the sampling frequency and distinguish between signaling and non-signaling frames by thir pulse width. A frame synchronization pulse which is one master clock wide designates a non-signaling frame, while a double wide sync pulse enables
Only transmit is on stand-by Only receive is on stand-by 4/17
FSX is TTL low FSR is TTL low
M5913
the signaling function. TSX is a timeslot strobe/buffer enable output which gates the PCM word onto the PCM highway when an external buffer is used to drive the line. Data is transmitted on the highway at DX on the first eight positive transitions of CLKX following the rising edge of FSX. Similarly, on the receive side, data is received on the first eight falling edges of CLKR. The frequency of CLKX and CLKR is selected by the CLKSEL pin to be either 1.536, 1.544 or 2.048MHz. No other frequency of operation is allowed in the fixed data rate mode. Variable Data Rate Mode Variable data rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather than to VBB. It employes master clocks CLKX and CLKR, bit clocks DCLKR and DCLKX and frame synchronization clocks FSR and FSX. Variable data rate timing allows for a flexible data frequency. It provides the ability to vary the frequency of the bit clocks, from 64kHz to 4096MHz. Master clocks inputs are still restricted to 1.536, 1.544, or 2.048MHz. In this mode, DCLKR and DCLKX become the data clocks for the receive and transmit PCM highways. While FSX is high, PCM data from DX is transmitted onto the highway on the next eight consecutive positive transitions of DCLKX. Similarly, while FSR is high, each PCM bit from the highway is received by D R on the next eight consecutive negative transitions of DCLKR. On the transmit side, the PCM word will be repeated in all remaining timeslots in the 125s frame as long as DCLKX is pulsed and FSX is held high. This feature allows the PCM word to be transmitted to the PCM highway more than once per frame, if desired, and is only available in the variable data rate mode. Conversely, signaling is only allowed in the fixed data rate mode since the variable mode provides no means with which to specify a signaling frame. Precision Voltage References No external components are required with the combochip to provide the voltage reference function. Voltage references are generated on-chip and are calibrated during the manufacturing process. The technique use the bandgap principle to derive a temperature and bias stable reference voltage. These references determine the gain and dynamic range characteristics of the device. Separate references are supplied to the transmit and receive sections. Transmit and receive section are trimmed independently in the filter stages to a final precision value. With this method the combochip can achieve manufacturing tolerances of typically 0.04dB in absolute gain for each half channel, providing the user a significant margin for error in other board components. Conversion Laws The M5913 is designed to operate in both -law and A-law systems. The user can select either conversion law according to the voltage present on the SIGX/ASEL pin . In each case the coder and decoder process a companded 8-bit PCM word following CCITT recommandation G.711 for -law and A-law conversion. If A-law operation is desired, SIGX should be tied to VBB. Thus, signaling is not allowed during A-law operation. If = 255-law operation is selected, then SIGX is a TTL level input which modifies the LSB on the PCM output in signaling frames TRANSMIT OPERATION Transmit Filter The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational amplifier. This operational amplifier has a common mode range of 2.17V, a maximum DC offset of 25mV, a minimum voltage gain of 5000, and a unity gain bandwidth of typically 1MHz. Gain of up to 20dB can be set without degrading the performance of the filter. The load impedance to ground (GRDA) at the amplifier output (GSX) must be greater than 10k in parallel high less than 50pF. The input signal on lead VFXI+ can be either AC or DC coupled. The input op amp can also be used in the inverting mode or differential amplifier mode (see figure 3). A low pass anti-aliasing section is included onchip. This section typically provides 35dB attenuation at the sampling frequency. No external components are required to provide the necessary anti-aliasing function for the switched capacitor section of the transmit filter. The passband section provides flatness and stopband attenuation which fulfills the AT&T D3/D4 channel bank transmission specification and CCITT recommendation G.712. The M5913 specifications meet or exceed digital class 5 central office switching systems requirements. The transmit filter transfer characteristics and specifications will be within the limits shown the relative table. A high pass section configuration was chosen to reject low frequency noise from 50 and 60Hz power lines, 17Hz European electric railroads, ringing frequencies and their harmonics, and other low frequency noise. Even though there is high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200Hz. This feature allows the use of low-cost transformer hybrids without external components.
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Figure 3: Transmit Filter Gain Adjustment. an internal sample and hold capacitor. This sample is then transferred to the receive filter. Receive Filter The receive section of the filter provides passband flatness and stopband rejection which fulfills both the AT&T D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin X)/X response of such decoders. The receive filter characteristics and specifications are shown in the relative table. Receive Output Power Amplifiers A balanced output amplifier is provided in order to allow maximum flexibility in output configuration. Either of the two outputs can be used single ended (referenced to GRDA) to drive single ended loads. Alternatively, the differential output will drive a bridged load directly. The output stage is capable of driving loads as low as 300 ohms single ended to a level of 12dBm or 600 ohms differentially to a level of 15dBm. The receive channel transmission level may be adjusted between specified limits by manipulation of the GSR input. GSR is internally connected to an analog gain setting network. When GSR is strapped to PWRO-, the receive level is minimized; when it is tied to PWRO+, the level is minimized. The output transmission level interpolates between 0 and -12dB as GSR is interpolated (with potentiometer) between PWRO- and PWRO+. The use of the output gain set is illustrated in figure 4. Transmission levels are specified relative to the receive channel output under digital milliwatt conditions, that is, when the digital input at DR is the eight-code sequence specified in CCITT recommendation G.711.
Encoding The encoder internally samples the output of the transmit filter and holds each sample on an internal sample and hold capacitor. The encoder then performs an analog to digital conversion on a switched capacitor array. Digital data representing the sample is transmitted on the first eight data clock bits of the next frame. An on-chip autozero circuit corrects for DC-offset on the input signal to the encoder. This autozero circuit uses the sign bit averaging technique. In this way, all DC offset is removed from the encoder input waveform. RECEIVE OPERATION Decoding The PCM word at the DR lead is serially fetched on the first eight data clock bits of the frame. A D/A conversion is performed on the digital word and the corresponding analog sample is held on Figure 4: Gain Setting Configuration.
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M5913
OUTPUT GAIN SET: DESIGN CONSIDERATIONS (refer to figure 4) PWRO+ and PWRO- are low impedance complementary outputs. The voltages at the nodes are: VO at PWRO+ VO at PWRO VO = VO+ VO- (total differential response) R1 and R2 are a gain setting resistor network with the center tap connected to the GSR input. A value greater than 10K and less than 100K for R1 + R2 is recommended because: a) The parallel combination of R1 + R2 and RL sets the total loading. b) The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant which has to be minimized to avoid inaccuracies. If VA represents the output voltage without any gain setting network connected, you can have: VO = AVA 1 + (R1 / R2) where A = 4 + (R1 / R2) For design purposes, a useful form is R1/R2 as a function of A. 4A - 1 R1 / R2 = 1 -A (allowable values for A are those which make R1/R2 positive) Examples are: If A = 1 (maximum output), then R1/R2 = or V(GSR) = VO; i.e., GSR is tied to PWRO+ If A = 1/2. then R1/R2 = 2 If A = 1/4 (minimum output) then R1/R2 = 0 or V(GSR ) = VO+; i.e., GSR is tied to PWRO+
DC CHARACTERISTICS (Tamb = 0 to 70oC, VCC = +5V 5%, VBB = - 5V 5%, GRDA = 0V,unless otherwise specified) Typical values are for Tamb = 25oC and nominal power supply values.
Symbol DIGITAL INTERFACE IIL IIH VIL VIH VOL VOH VILO VIIO VIHO C OX C IN
Notes: 1. VIN is the voltage on any digital pin. 2. SIGX and DCLKR are TTL level inputs between GRDD and VCC; they are also pinstraps for mode selection when tied to VBB. Under these conditions VILO is the input low voltage requirement. 3. Timing parameters are guaranteed based on a 100pF load capacitance. Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF.
Parameter Low Level Input Current High Level Input Current Input Low Voltage, Except CLKSEL Input High Voltage, Except CLKSEL Output Low Voltage Output High Voltage Input Low Voltage, CLKSEL (note 2) Input Intermediate Voltage, CLKSEL Input High Voltage, CLKSEL Digital Output Capacitance (note 3) Digital Input Capacitance
Test Conditions GRDD VIN VIL (note 1) VIH VIN VCC
Min.
Typ.
Max. 10 10 0.8
Unit A A V V V V
2.0 IOL = 3.2mA at DX, TSX and SIGR IOH = 9.6mA at DX IOH = 1.2mA at SIGR 2.4 VBB GRDD -0.5 VCC 0.5 5 5 10 VBB + 0.5 0.5 VCC 0.4
V V V pF pF
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DC CHARACTERISTICS (continued)
Symbol ICC1 IBB1 ICC0 IBB0 ICCS IBBS PD1 PD0 PST IBX1 R IXI VOSXI CMRR AVOL fC VOXI CLXI RLXI R ORA VOSRA C LRA Parameter VCC Operating Current VBB Operating Current VCC Power Down Current VBB Power Down Current VCC Standby Current VBB Standby Current Operating Power Dissipation Power Down Dissipation Standby Power Dissipation Input Leakage Current, VFXI+, VFXIInput Resistance, VFXI+, VFXIInput Offset Voltage, VFXI+, VFXICommon Mode Rejection, VFXI+, VFXIDC Open Loop Voltage Gain, GSX Open Loop Unity Gain Bandwidth, GSX Output Voltage Swing GSX Load Capacitance, GSX Minimum Load Resistance, GSX Output Resistance, PWRO+, PWROSingle-ended Output DC Offset, PWRO+, PWROLoad Capacitance, PWRO+, PWRORelative to GRDA -150 10 1 75 150 100 RL 10k - 2.17 -2.17V VIN 2.17V RL = 10K 55 5000 20.000 1 2.17 50 MHz V pF k mV pF PDN VIL ; after 10s FSX, FSR VIL ; after 30ms -2.17V VIN 2.17V 10 25 PDN VIL ; after 10s PDN VIL ; after 10s FSX, FSR VIL ; after 30ms FSX, FSR VIL ; after 30ms Test Conditions Min. Typ. 6 6 40 40 300 40 60 0.4 1.7 Max 10 9 300 300 600 300 100 3 5 100 Unit mA mA A A A A mW mW mW nA M mV dB POWER DISSIPATION All measurements made at fDCLK = 2.048MHz, outputs unloaded
ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE
ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE
AC CHARACTERISTICS - TRANSMISSION PARAMETERS Unless otherwie noted, the analog input is a 0dBm0, 1020Hz sine wave1. Input amplifier is set for unity gain, noninverting. The digital inputs is a PCM bit stream generated by passing a 0dBm0, 1020Hz sine wave through an ideal encoder. Receive output is measured single ended, maximum gain configuration2. All output levels are (sin X)/X corrected.
Symbol EmW EmWTS Parameter Encoder Milliwatt Response (transmit gain tolerance) EmW Variation with Temperature and Supplies Digital Milliwatt Response (receive gain tolerance) DmW Variation with Temperature and Supplies Zero Transmission Level Point Transmit Channel (0dBm0) -law Zero Transmission Level Point Transmit Channel (0dBm0) A-law Zero Receive Level Point Receive Channel (0dBm0) -law Zero Transmission Level Point Transmit Channel (0dBm0)) A-law Test Conditions Tamb = 25C, VBB = - 5V, VCC = + 5V 5% Supplies, 0 to 70C Relative to Nominal Conditions Tamb = 25C ; VBB = - 5V, VCC = + 5V 5%, 0 to 70C Referenced to 600 Referenced to 900 Referenced to 600 Referenced to 900 Referenced to 600 Referenced to 900 Referenced to 600 Referenced to 900 Min. -0.15 -0.12 Typ. 0.04 Max. +0.15 +0.12 Unit dBm0 dB GAIN AND DYNAMIC RANGE
DmW DmW TS 0TLP 1X 0TLP 2X 0TLP1R 0TLP2R
-0.15 -0.08
0.04
+0.15 +0.08
dBm0 dB dBm dBm dBm dBm dBm dBm dBm dBm
+ 2.76 + 1.00 + 2.79 + 1.03 + 5.76 + 4.00 + 5.79 + 4.03
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AC CHARACTERISTICS (continued)
Symbol GT1X Parameter Transmit Gain Tracking Error Sinusoidal Input; -law Transmit Gain Tracking Error Sinusoidal Input; A-law Receive Gain Tracking Error Sinusoidal Input; -law Receive Gain Tracking Error Sinusoidal Input; A-law Test Conditions + 3 to - 40dBm0 - 40 to - 50dBm0 - 50 to - 55dBm0 + 3 to - 40dBm0 - 40 to - 50dBm0 - 50 to - 55dBm0 + 3 to - 40dBm0 - 40 to - 50dBm0 - 50 to - 55dBm0 + 3 to - 40dBm0 - 40 to - 50dBm0 - 50 to - 55dBm0 VFXI+ = GRDA, VFXI- = GSX VFXI+ = GRDA, VFXI- = GSX 6 th Frame Signaling VFXI+ = GRDA, VFXI- = GSX D R = 11111111 Measure at PWRO+ Input to D R is 0 code with Sign Bit Toggle at 1KHz Rate D R = Lowest Positive Decode Level CCITT G.712.4.2 Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at DX Idle Channel ; 200mV P-P Signal on Supply ; 0 to 50kHz, Measure at DX Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz Idle Channel ; 200mV P-P Signal on Supply ; Measure Narrow Band at PWRO+ Single Ended, 0 to 50kHz VFXI+ = 0dBm0, 1.02kHz, D R = Lowest Positive Decode Level, Measure at PWRO+ D B = 0dBm0, 1.02kHz, VFXI+ = GRDA, Measure at DX - 40 0 13 (note 3) 1 1 -90 Min. Typ. Max. 0.2 0.4 1.0 0.2 0.4 1.0 0.2 0.4 1.0 0.2 0.4 1.0 13 18 - 80 9 10 - 81 - 50 Unit dB dB dB dB dB dB dB dB dB dB dB dB dBrnc0 dBrnc0 dBrnc0 dBrnc0 dBm0p dB0p dBm0 dB GAIN TRACKING Reference Level = - 10dBm0
GT2X
GT1R
GT2R
NOISE N XC1 N XC2 NXP NRC1 NRC2 NRP N SF PSRR1 Transmit Noise, C-message Weighted Transmit Noise, C-message Weighted with Eighth Bit Signaling Transmit Noise, Psophometrically Weighted Receive Noise, C-message Weighted: Quiet Code Receive Noise, C-message Weighted: Sign Bit Toggle Receive Noise, Psophometrically Weighted Single Frequency NOISE End to End Measurement VCC Power Supply Rejection, Transmit Channel VBB Power Supply Rejection, Transmit Channel VCC Power Supply Rejection, Receive Channel
PSRR2
- 40
dB
PSRR3
- 40
dB
PSRR4
VBB Power Supply, Rejection Receive Channel
- 40
dB
CTTR
Crosstalk, Transmit to Receive, Single Ended Outputs Crosstalk, Receive to Transmit, Single Ended Outputs
- 80
dB
CTRT
- 80
dB
Notes: 1. 0dBm0 is defined as the zero reference point of the channel under test (0TLP). This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrmst (Law) dual 1.068 Vrmst or a output 1.516 Vrmst (A-Law) 2. Unity gain input amplifier : GSX is connected to VFXI, Signal input VFXI+; Maximum gain output amplifier: GSR is connected to PWRO, output to PWRO+. 3. Noise free: DX PCM Code stable at 01010101.
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A.C. CHARACTERISTICS (continued)
Symbol Parameter DISTORTION Transmit Signal to Distortion, -law SD1X Sinusoidal Input; CCITT G.712-method 2 SD2X Transmit Signal to Distortion, A-law Sinusoidal Input, CCITT G.712-method 2 SD1R Transmit Signal to Distortion, -law Sinusoidal Input , CCITT G.712-method 2 Receive Signal to Distortion, A-law SD2R Sinusoidal Input; CCITT G.712-method 2 DP X1 Transmit Single Frequency Distortion Products Receive Single Frequency Distortion DPR1 Products Intermodulation Distortion, IMD1 End to End Measurement Intermodulation Distortion, IMD2 End to End Measurement SOS Spurious Out of Band Signals, End to End Measurement SIS Spurious in Band Signals, End to End Measurement Transmit Absolute Delay DAX Test Conditions 0 VFXI+ - 30dBm0 - 40dBm0 - 45dBm0 0 VFXI+ - 30dBm0 - 40dBm0 - 45dBm0 0 VFXI+ - 30dBm0 - 40dBm0 - 45dBm0 0 VFXI+ - 30dBm0 - 40dBm0 - 45dBm0 AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal AT & T Adivisory # 64 (3.8) 0dBm0 Input Signal CCITT G.712 (7.1) CCITT G.712 (7.2) CCITT G.712 (6.1) CCITT G.712 (9) Fixed Data Rate CLKX = 2.048MHz, 0dBm0, 1.02kHz Signal at VFXI+ Measure at D X f = 500 - 600Hz f = 600 - 1000Hz f = 1000 - 2600Hz f = 2600 - 2800Hz Fixed data rate, CLKR = 2.048MHz; Digital input is DMW codes. Measure at PWRO+ f = 500 - 600Hz f = 600 - 1000Hz f = 1000 - 2600Hz f = 2600 - 2800Hz 300 Min. 36 30 25 36 30 25 36 30 25 36 30 25 - 46 - 46 - 35 - 49 - 30 - 40 Typ. Max. Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm0 dBm0 s
DDX
Transmit Differential Envelope Delay Relative to DAX
170 95 45 80 190
DAR
Receive Absolute Delay
s s s s s
D DR
Receive Differential Envelope Delay Relative to DAR
10 10 85 110
s s s s
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A.C. CHARACTERISTICS (continued) TRANSMIT CHANNEL TRANSFER CHARACTERISTICS (Input amplifier is set for unity gain, noninverting; maximum gain output.)
Symbol GRX Parameter Gain Relative to Gain at 1.02 kHz 16.67Hz 50Hz 60Hz 200Hz 300 to 3000Hz 3300Hz 3400Hz 4000Hz 4600Hz and Above Test Conditions 0 dBm0 Signal Input at VFXI+ Min. Typ. Max. - 30 - 25 - 23 - 0.125 + 0.125 + 0.03 - 0.10 - 14 - 32 Unit dB dB dB dB dB dB dB dB dB
- 1.8 - 0.125 - 0.35 - 0.7
Figure 5: Transmit Filter
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A.C. CHARACTERISTICS (continued) RECEIVE CHANNEL TRANSFER CHARACTERISTICS
Symbol GRR Parameter Gain Relative to Gainat 1.02kHz below 200Hz 200Hz 300 to 3000Hz 3300Hz 3400Hz 4000Hz 4600Hz and Above Test Conditions 0dBm0 Signal Input at D R Min. Typ. Max. + 0.125 + 0.125 + 0.125 + 0.03 - 0.1 - 14 - 30 Unit dB dB dB dB dB dB dB
- 0.5 - 0.125 - 0.35 - 0.7
Figure 6: Receive Filter
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M5913
AC CHARACTERISTICS - TIMING PARAMETERS
Symbol Parameter Test Conditions CLOCK SECTION Clock Period, CLKX, CLKR fCLKX = fCLKR = 2.048MHz tCY tCLK Clock Pulse Width CLKX, CLKR 1 Data Clock Pulse Width 64kHz fDCLK 2.048MHz tDCLK Clock Duty Cycle CLKX, CLKR tCDC Clock Rise and Fall Time tr, tf TRANSMIT SECTION, FIXED DATA RATE MODE2 tDZX Data Enabled on TS Entry 0 < CLOAD < 100pF Data Delay from CLKX 0 < CLOAD < 100pF tDDX Data Float on TS Exit C LOAD = 0 tHZX tSON Timeslot X to Enable 0 < CLOAD < 100pF Timeslot X to Disable C LOAD = 0 tSOFF tFSD Frame Sync Delay Signal Setup Time tSS Signal Setup Time tSH RECEIVE SECTION, FIXED DATA RATE MODE Receive Data Setup tDSR tDHR Receive Data Hold Frame Sync Delay tFSD tSIGR SIGR Update TRANSMIT SECTION, FIXED DATA RATE MODE2 tTSDX Timeslot Delay from DCLKX Frame Sync Delay tFSD Data Delay from DCLKX 0 < CLOAD < 100pF tDDX tDON Timeslot to D X Active 0 < CLOAD < 100pF Timeslot to D X Inactive 0 < CLOAD < 100pF tDOFF fDX Data Clock Frequency Data Delay from FSX tTSDX = 80ns tDFSX RECEIVE SECTION, FIXED DATA RATE MODE Timeslot Delay from DCLKR tTSDR tFSD Frame Sync Delay Receive Data Setup Time tDSR Receive Data Hold Time tDHR Data Clock Frequency tDR tSER Timeslot End Receive Time 64KB OPERATION, VARIABLE DATA RATE MODE Transmit Frame Sync Minimum FSX is TTL high for tFSLX Downtime remainder of frame Receive Frame Sync Miniumum FSR is TTL high for tFSLR Downtime remainder of frame Data Clock Pulse Width tDCLK
Notes: 1. Devices are available wich operate at data rates up to 4.096MHz; the minimum data clock pulse width for these devices is 110ns 2. Timing parameters tDZX, tHZX, and tSOFF are referenced to a high impedance state.
Min. 488 195 195 40 5 0 0 60 0 50 0 0 0 10 60 0 0 -80 0 0 0 0 64 0 -80 0 10 60 64 0 488 1952 10
Typ.
Max.
Unit ns ns ns % ns ns ns ns ns ns ns ns ns ns ns ns s ns ns ns ns ns KHz ns ns ns ns ns kHz ns ns ns s
50
60 30 145 145 190 145 190 120
120 2 80 120 100 50 80 1 2048 140 80 120
20481
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M5913
WAVEFORMS: Fixed Data Rate Timing - Transmit Timing
NOTE: All timing parameters referenced to VIH and VIL except tDZX, tSOFF and tHZX which reference a high impedance state.
Receive Timing
NOTE: All timing parameters referenced to VIH and VIL
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M5913
VARIABLE DATA RATE TIMING
AC Timing Input, Output Waveform
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M5913
DIP20 PACKAGE MECHANICAL DATA
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.053 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 mm TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
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M5913
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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